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As global economy is affected by COVID-19, the initiative offers few free and affordable educational services to engineering undergraduates and graduates! Our offices will remain closed during lock down period. Request all of you to work from home. Stay home and stay safe!

Who We Are

A Little Brief About Us

1 Rupee S T ( Semiconductor Training @ Rs. 1) is initiative of Vaibbhav Taraate. He is Entrepreneur and Mentor at “Semiconductor Training @ Rs.1”.

He has over 15 Years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL.

He holds a BE (Electronics) degree from Shivaji University, Kolhapur in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his MTech (Aerospace Control and Guidance) in 1999 from IIT Bombay.

Interactive Video Sessions

Published Books with Springer

BookAuthority Awards

Book Cover of Vaibbhav Taraate - Advanced HDL Synthesis and SOC Prototyping: RTL Design using Verilog
The best FPGA books of all time
Book Cover of Vaibbhav Taraate - Advanced HDL Synthesis and SOC Prototyping: RTL Design using Verilog
The best Prototyping books of all time
Book Cover of Vaibbhav Taraate - Logic Synthesis and SOC Prototyping: RTL Design using VHDL
BookAuthority Best New FPGA Books
Book Cover of Vaibbhav Taraate - Logic Synthesis and SOC Prototyping: RTL Design using VHDL
BookAuthority Best New Prototyping Books

We Provide Corporate Training and
FPGA Design Services.
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Success Key

Our Corporate Programs

  • High Speed digital Design
  • RTL Design Using Verilog
  • RTL Design Using VHDL

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Work Sample

Our Workshops

  • Design using FPGA with VHDL
  • Design using FPGA with Verilog
  • Digital Design and Practical applications

Click here to view all Workshops